The invention relates to integrated circit (IC) devices of the operational amplifier (op-amp) type which has a differential amplifier (diff-amp) input stage. Such devices are made to have a very low input offset voltage and, typically, include means for connecting a potentiometer which can be adjusted to further reduce the offset voltage to substantially zero. Offset voltage is defined as that voltage which must be applied between the input terminals through two equal resistors to obtain zero output voltage. Where the IC is designed to operate from a single V.sub.CC supply, the zero output voltage is replaced with V.sub.CC /2, or one half of the supply voltage. Typically, high performance IC's are rated at an offset voltage in the range of one or a few millivolts. In more stringently specified devices the value can be as low as a few tens of microvolts.
In the manufacture of IC op-amps it is common practice to perform a trim operation that reduces the offset voltage to bring it into specification. Also, the typical device circuitry to further reduce the offset voltage to any desired value. The manufacturing trim operation is commonly done at wafer sort where the individual IC chips are probed and tested to determine functionality. Then, only the good chips are assembled into a final package. During the wafer probing operation the working chips are typically trimmed to bring the offset voltage into specification. This trim is commonly done by zener zapping which is taught in Russell U.S. Pat. No. 4,618,833. In some cases zener zapping is replaced or augmented by the use of metal links which can be blown as a fuse or laser severed to produce a trim. The preferred circuit detailed in U.S. Pat. No. 4,618,833 is a BIFET.RTM. IC device. This is a registered trademark of NATIONAL SEMICONDUCTOR CORPORATION covering IC devices that include thin junction field effect transistors (JFETs). The teaching in this patent, which is assigned to the assignee of the present invention, is incorporated herein by reference.
While an IC can be wafer trimmed to produce a low offset voltage, it has been found that a shift can be produced by the final assembly. This is particularly true of BISFET.RTM. IC devices. It is thought that this is due to the presence of very thin JFET structures which are more strain sensitive than conventional IC components. Accordingly, it is desirable for an offset voltage trim to be accomplished after the IC is assembled.